module tb_backforward_coe_upgrade;
parameter length = 16;

reg clk;
reg rst_n;

reg signed [length-1:0] input_signal;
reg signed [length-1:0] error_distance;

wire signed [length-1:0] IS0;
wire signed [length-1:0] IS1;
wire signed [length-1:0] IS2;
wire signed [length-1:0] IS3;
wire signed [length-1:0] IS4;
wire signed [length-1:0] IS5;
wire signed [length-1:0] IS6;
wire signed [length-1:0] IS7;
wire signed [length-1:0] IS8;
wire signed [length-1:0] IS9;
wire signed [length-1:0] IS10;
wire signed [length-1:0] IS11;
wire signed [length-1:0] IS12;
wire signed [length-1:0] IS13;
wire signed [length-1:0] IS14;
wire signed [length-1:0] IS15;
wire signed [length-1:0] IS16;
wire signed [length-1:0] IS17;
wire signed [length-1:0] IS18;
wire signed [length-1:0] IS19;
wire signed [length-1:0] IS20;
wire signed [length-1:0] IS21;
wire signed [length-1:0] IS22;
wire signed [length-1:0] IS23;
wire signed [length-1:0] IS24;
wire signed [length-1:0] IS25;
wire signed [length-1:0] IS26;
wire signed [length-1:0] IS27;
wire signed [length-1:0] IS28;
wire signed [length-1:0] IS29;
wire signed [length-1:0] IS30;
wire signed [length-1:0] IS31;
wire signed [length-1:0] W0;
wire signed [length-1:0] W1;
wire signed [length-1:0] W2;
wire signed [length-1:0] W3;
wire signed [length-1:0] W4;
wire signed [length-1:0] W5;
wire signed [length-1:0] W6;
wire signed [length-1:0] W7;
wire signed [length-1:0] W8;
wire signed [length-1:0] W9;
wire signed [length-1:0] W10;
wire signed [length-1:0] W11;
wire signed [length-1:0] W12;
wire signed [length-1:0] W13;
wire signed [length-1:0] W14;
wire signed [length-1:0] W15;
wire signed [length-1:0] W16;
wire signed [length-1:0] W17;
wire signed [length-1:0] W18;
wire signed [length-1:0] W19;
wire signed [length-1:0] W20;
wire signed [length-1:0] W21;
wire signed [length-1:0] W22;
wire signed [length-1:0] W23;
wire signed [length-1:0] W24;
wire signed [length-1:0] W25;
wire signed [length-1:0] W26;
wire signed [length-1:0] W27;
wire signed [length-1:0] W28;
wire signed [length-1:0] W29;
wire signed [length-1:0] W30;
wire signed [length-1:0] W31;	

IS_reg
	#(length)
	IS_reg_u0
	(
		.clk 			(clk 			),
		.rst_n  		(rst_n 			),

		.input_signal	(input_signal	),

		.IS0			(IS0			),
		.IS1			(IS1			),
		.IS2			(IS2			),
		.IS3			(IS3			),
		.IS4			(IS4			),
		.IS5			(IS5			),
		.IS6			(IS6			),
		.IS7			(IS7			),
		.IS8			(IS8			),
		.IS9			(IS9			),
		.IS10			(IS10			),
		.IS11			(IS11			),
		.IS12			(IS12			),
		.IS13			(IS13			),
		.IS14			(IS14			),
		.IS15			(IS15			),
		.IS16			(IS16			),
		.IS17			(IS17			),
		.IS18			(IS18			),
		.IS19			(IS19			),
		.IS20			(IS20			),
		.IS21			(IS21			),
		.IS22			(IS22			),
		.IS23			(IS23			),
		.IS24			(IS24			),
		.IS25			(IS25			),
		.IS26			(IS26			),
		.IS27			(IS27			),
		.IS28			(IS28			),
		.IS29			(IS29			),
		.IS30			(IS30			),
		.IS31			(IS31			)
	);

backforward_coe_update
	#(length)
	backforward_coe_update_u0
	(
		.clk 		(clk 		),
		.rst_n      (rst_n 		),
		.IS0		(IS0		),
		.IS1		(IS1		),
		.IS2		(IS2		),
		.IS3		(IS3		),
		.IS4		(IS4		),
		.IS5		(IS5		),
		.IS6		(IS6		),
		.IS7		(IS7		),
		.IS8		(IS8		),
		.IS9		(IS9		),
		.IS10		(IS10		),
		.IS11		(IS11		),
		.IS12		(IS12		),
		.IS13		(IS13		),
		.IS14		(IS14		),
		.IS15		(IS15		),
		.IS16		(IS16		),
		.IS17		(IS17		),
		.IS18		(IS18		),
		.IS19		(IS19		),
		.IS20		(IS20		),
		.IS21		(IS21		),
		.IS22		(IS22		),
		.IS23		(IS23		),
		.IS24		(IS24		),
		.IS25		(IS25		),
		.IS26		(IS26		),
		.IS27		(IS27		),
		.IS28		(IS28		),
		.IS29		(IS29		),
		.IS30		(IS30		),
		.IS31		(IS31		),

		.error_distance	(error_distance),

		.W0			(W0			),
		.W1			(W1			),
		.W2			(W2			),
		.W3			(W3			),
		.W4			(W4			),
		.W5			(W5			),
		.W6			(W6			),
		.W7			(W7			),
		.W8			(W8			),
		.W9			(W9			),
		.W10		(W10		),	
		.W11		(W11		),	
		.W12		(W12		),	
		.W13		(W13		),	
		.W14		(W14		),	
		.W15		(W15		),	
		.W16		(W16		),	
		.W17		(W17		),	
		.W18		(W18		),	
		.W19		(W19		),	
		.W20		(W20		),	
		.W21		(W21		),	
		.W22		(W22		),	
		.W23		(W23		),	
		.W24		(W24		),	
		.W25		(W25		),	
		.W26		(W26		),	
		.W27		(W27		),	
		.W28		(W28		),	
		.W29		(W29		),	
		.W30		(W30		),	
		.W31		(W31		)	

	);

always #5 clk = ~clk;

initial begin
	clk = 0;
	rst_n = 0;
	#15
	rst_n = 1;
	input_signal = 32765;
	error_distance = 32765;
	#320
	input_signal = 0;
	#100
	$display("end");
end

initial	begin
	$monitor($realtime,"\tW31 = %d,\tIS31 = %d",W31, IS31);
end

endmodule

